General Description
The Evaluation Board user guide describes the operational use of the RTQ2533W evaluation board as a reference design for demonstration and evaluation of the RTQ2533W, a high-current, ultra-low noise, ultra low-dropout (LDO) linear regulator.
Included in this user guide are setup and operating instructions, thermal and layout guidelines, a printed circuit board (PCB) layout, a schematic diagram, and a bill of materials (BOM). For more detail information, please refer to the RTQ2533W datasheet.
Performance Specification Summary
Summary of the RTQ2533W Evaluation Board performance specificiaiton is provided in Table 1. The ambient temperature is 25°C.
Table 1. RTQ2533W Evaluation Board Performance Specification Summary
Specification
|
Test Conditions
|
Min
|
Typ
|
Max
|
Unit
|
Input Voltage Range
|
|
1.1
|
1.1
|
6.5
|
V
|
Output Current
|
|
0
|
--
|
3
|
A
|
Output Voltage Range
|
Using ecternal resistors
|
0.8
|
0.8
|
5.5
|
V
|
Line Regulation
|
IOUT = 1mA, 1.1V ≤ VIN ≤ 6.5V
|
--
|
0.05
|
--
|
%/V
|
Load Regulation
|
1mA ≤ IOUT ≤ 3A
|
--
|
0.08
|
--
|
%/A
|
Dropout Voltage
|
VIN = 1.1V to 6.5V, IOUT = 3A,
VFB = 0.8V - 3%
|
--
|
110
|
180
|
mV
|
Power-up Procedure
Suggestion Required Equipments
- RTQ2533W Evaluation Board
- DC power supply capable of at least 6.5V and 3A
- Electronic load capable of 3A
- Function generator
- Oscilloscope
Quick Start Procedures
The Evaluation Board is fully assembled and tested. Follow the steps below to verify board operation. Do not turn on supplies until all connections are made. When measuring the output voltage ripple, care must be taken to avoid a long ground lead on the oscilloscope probe. Measure the output voltage ripple by touching the probe tip and groundring directly across the last output capacitor.
Proper measurement equipment setup and follow the procedure below.
1) With power off, connect the input power supply to VIN and GND pins.
2) With power off, connect the electronic load between the VOUT and nearest GND pins.
3) Turn on the power supply at the input. Make sure that the input voltage does not exceeds 6V on the Evaluation Board.
4) Check for the proper output voltage using a voltmeter.
5) Once the proper output voltage is established, adjust the load within the operating ranges and observe the output voltage regulation, quiescent current, dropout voltage, PSRR, noise and other performance.
Detailed Description of Hardware
Headers Description and Placement
Carefully inspect all the components used in the EVB according to the following Bill of Materials table, and then make sure all the components are undamaged and correctly installed. If there is any missing or damaged component, which may occur during transportation, please contact our distributors or e-mail us at evb_service@richtek.com.
Test Points
The EVB is provided with the test points and pin names listed in the table below.
Test Point/
Pin Name
|
Function
|
VOUT
|
Output of the regulator.
|
VIN
|
Supply input pin.
|
BIAS
|
Bias input pin.
|
PG
|
Power good sense pin.
|
GND
|
System ground pin.
|
EN
|
Enable sense pin.
|
VOUT-S1/VOUT-S2
|
Waveform sense pin for resistor R3.
|
JP1
|
User can decide EN pin connected to high or low.
|
JP3
|
Output voltage setting pin.
|
JP4
|
Feedback voltage sense pin.
|
J5
|
Short to by-pass resistor R3.
|
Bill of Materials
VIN = 1.1V to 6.5V, VOUT = 0.8V to 5.5V, IOUT = 2A
|
Reference
|
Count
|
Part Number
|
Value
|
Description
|
Package
|
Manufacturer
|
U1
|
1
|
RTQ2533WGQW(2)
|
RTQ2533WGQW(2)
|
LDO
|
VQFN-20L 3.5x3.5
|
RICHTEK
|
C-NR/SS, CFF1
|
2
|
GRM033R71E103KE14
|
10nF
|
Capacitor, ceramic,
50V, X7R
|
0603
|
MURATA
|
C3, C11
|
2
|
GRM21BR61A476ME15
|
47μF
|
Capacitor, ceramic,
10V, X5R
|
0805
|
MURATA
|
C9, C12
|
2
|
0603B104K500CT
|
0.1μF
|
Capacitor, ceramic,
50V, X7R
|
0603
|
WALSIN
|
R-SNS, R3
|
2
|
WR06X000 PTL
|
0
|
Resistor, Chip
|
0603
|
WALSIN
|
REN1, RPG1
|
2
|
WR06X1003FTL
|
100k
|
Resistor, Chip
|
0603
|
WALSIN
|
Typical Applications
EVB Schematic Diagram
1. The capacitance values of the input and output capacitors will influence the input and output voltage ripple.
2. MLCC capacitors have degrading capacitance at DC bias voltage, and especially smaller size MLCC capacitors will have much lower capacitance.
3. VOUT select pin settings of JP3 please refer to Table 2.
Table 2. VOUT Select Pin Settings for Different Targets
VOUT (V)
|
50mV
|
100mV
|
200mV
|
400mV
|
800mV
|
1.6V
|
|
VOUT (V)
|
50mV
|
100mV
|
200mV
|
400mV
|
800mV
|
1.6V
|
0.8
|
Open
|
Open
|
Open
|
Open
|
Open
|
Open
|
|
2.4
|
Open
|
Open
|
Open
|
Open
|
Open
|
GND
|
0.85
|
GND
|
Open
|
Open
|
Open
|
Open
|
Open
|
|
2.45
|
GND
|
Open
|
Open
|
Open
|
Open
|
GND
|
0.9
|
Open
|
GND
|
Open
|
Open
|
Open
|
Open
|
|
2.5
|
Open
|
GND
|
Open
|
Open
|
Open
|
GND
|
0.95
|
GND
|
GND
|
Open
|
Open
|
Open
|
Open
|
|
2.55
|
GND
|
GND
|
Open
|
Open
|
Open
|
GND
|
1
|
Open
|
Open
|
GND
|
Open
|
Open
|
Open
|
|
2.6
|
Open
|
Open
|
GND
|
Open
|
Open
|
GND
|
1.05
|
GND
|
Open
|
GND
|
Open
|
Open
|
Open
|
|
2.65
|
GND
|
Open
|
GND
|
Open
|
Open
|
GND
|
1.1
|
Open
|
GND
|
GND
|
Open
|
Open
|
Open
|
|
2.7
|
Open
|
GND
|
GND
|
Open
|
Open
|
GND
|
1.15
|
GND
|
GND
|
GND
|
Open
|
Open
|
Open
|
|
2.75
|
GND
|
GND
|
GND
|
Open
|
Open
|
GND
|
1.2
|
Open
|
Open
|
Open
|
GND
|
Open
|
Open
|
|
2.8
|
Open
|
Open
|
Open
|
GND
|
Open
|
GND
|
1.25
|
GND
|
Open
|
Open
|
GND
|
Open
|
Open
|
|
2.85
|
GND
|
Open
|
Open
|
GND
|
Open
|
GND
|
1.3
|
Open
|
GND
|
Open
|
GND
|
Open
|
Open
|
|
2.9
|
Open
|
GND
|
Open
|
GND
|
Open
|
GND
|
1.35
|
GND
|
GND
|
Open
|
GND
|
Open
|
Open
|
|
2.95
|
GND
|
GND
|
Open
|
GND
|
Open
|
GND
|
1.4
|
Open
|
Open
|
GND
|
GND
|
Open
|
Open
|
|
3
|
Open
|
Open
|
GND
|
GND
|
Open
|
GND
|
1.45
|
GND
|
Open
|
GND
|
GND
|
Open
|
Open
|
|
3.05
|
GND
|
Open
|
GND
|
GND
|
Open
|
GND
|
1.5
|
Open
|
GND
|
GND
|
GND
|
Open
|
Open
|
|
3.1
|
Open
|
GND
|
GND
|
GND
|
Open
|
GND
|
1.55
|
GND
|
GND
|
GND
|
GND
|
Open
|
Open
|
|
3.15
|
GND
|
GND
|
GND
|
GND
|
Open
|
GND
|
1.6
|
Open
|
Open
|
Open
|
Open
|
GND
|
Open
|
|
3.2
|
Open
|
Open
|
Open
|
Open
|
GND
|
GND
|
1.65
|
GND
|
Open
|
Open
|
Open
|
GND
|
Open
|
|
3.25
|
GND
|
Open
|
Open
|
Open
|
GND
|
GND
|
1.7
|
Open
|
GND
|
Open
|
Open
|
GND
|
Open
|
|
3.3
|
Open
|
GND
|
Open
|
Open
|
GND
|
GND
|
1.75
|
GND
|
GND
|
Open
|
Open
|
GND
|
Open
|
|
3.35
|
GND
|
GND
|
Open
|
Open
|
GND
|
GND
|
1.8
|
Open
|
Open
|
GND
|
Open
|
GND
|
Open
|
|
3.4
|
Open
|
Open
|
GND
|
Open
|
GND
|
GND
|
1.85
|
GND
|
Open
|
GND
|
Open
|
GND
|
Open
|
|
3.45
|
GND
|
Open
|
GND
|
Open
|
GND
|
GND
|
1.9
|
Open
|
GND
|
GND
|
Open
|
GND
|
Open
|
|
3.5
|
Open
|
GND
|
GND
|
Open
|
GND
|
GND
|
1.95
|
GND
|
GND
|
GND
|
Open
|
GND
|
Open
|
|
3.55
|
GND
|
GND
|
GND
|
Open
|
GND
|
GND
|
2
|
Open
|
Open
|
Open
|
GND
|
GND
|
Open
|
|
3.6
|
Open
|
Open
|
Open
|
GND
|
GND
|
GND
|
2.05
|
GND
|
Open
|
Open
|
GND
|
GND
|
Open
|
|
3.65
|
GND
|
Open
|
Open
|
GND
|
GND
|
GND
|
2.1
|
Open
|
GND
|
Open
|
GND
|
GND
|
Open
|
|
3.7
|
Open
|
GND
|
Open
|
GND
|
GND
|
GND
|
2.15
|
GND
|
GND
|
Open
|
GND
|
GND
|
Open
|
|
3.75
|
GND
|
GND
|
Open
|
GND
|
GND
|
GND
|
2.2
|
Open
|
Open
|
GND
|
GND
|
GND
|
Open
|
|
3.8
|
Open
|
Open
|
GND
|
GND
|
GND
|
GND
|
2.25
|
GND
|
Open
|
GND
|
GND
|
GND
|
Open
|
|
3.85
|
GND
|
Open
|
GND
|
GND
|
GND
|
GND
|
2.3
|
Open
|
GND
|
GND
|
GND
|
GND
|
Open
|
|
3.9
|
Open
|
GND
|
GND
|
GND
|
GND
|
GND
|
2.35
|
GND
|
GND
|
GND
|
GND
|
GND
|
Open
|
|
3.95
|
GND
|
GND
|
GND
|
GND
|
GND
|
GND
|
Measure Result
Power Up Response
|
Output Noise vs. Frequency and Output Voltage
|
|
|
PSRR vs. Frequency and Iout
|
Load Transient Response
|
|
|
Dropout Voltage vs. Output Current
|
OCP
|
|
|
Bode plot
|
|
|
|
Note: When measuring the input or output voltage ripple, care must be taken to avoid a long ground lead on the oscilloscope probe. Measure the output voltage ripple by touching the probe tip directly across the output capacitor.
Evaluation Board Layout
Figure 1 to Figure 4 are RTQ2533W Evaluation Board layout. This board is constructed on four-layer PCB, outer layers with 1 oz. Cu and inner layers with 1 oz. Cu.
Figure 1. Top View (1st layer)
Figure 2. PCB Layout—Inner Side (2nd Layer)
Figure 3. PCB Layout—Inner Side (3rd Layer)
Figure 4. Bottom View (4th Layer)