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JPDC Analog Engineer (Senior/Principal)

Location: Tokyo, Japan

Job Description & Responsibilities

  • Design of optimized analog blocks meeting functional, cost and low power constraints and ensure spec. compliance
  • Design, verification, and simulation of analog blocks of mixed signal IC
  • Interpret target specifications to achieve system and design strategy for mixed signal IC products
  • Guide layout team to ensure quality of layout
  • Contribute to analog, digital, layout design review and verification review
  • Drive silicon debugging and design characterization
  • Work closely with test engineer and DfT engineer to create test strategy and smooth test program ramp-up
  • Coach and mentor less experience team members

Key Performance Measures

  • Capability to create block level design strategy from the IC specification, to fulfill cost, area and power requirements
  • First time right design, on time and according to design specification
  • Demonstrate knowledge sharing and mentoring of young analog design engineers
  • Timely and accurate documentation


Degree of electronics engineering or a related discipline

Knowledge, Skills and Experience

  • Essential
    • At least 5 years’ experience in analog design
    • Strong knowledge and skill of transistor level circuit design and system level design
    • Power management IC, Switching regulator, LDO, battery charger, audio amplifier design experience
    • Thorough knowledge of Cadence Virtuoso, Spectre/Hspice simulation
    • Ability to work both independently and as part of a team
    • Good communication skill in English
    • Desirable
      • Analog or digital design skill
      • Communication skill in Mandarin or Japanese