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JPDC Digital Engineer (Senior/Principal)

Location: Tokyo, Japan

Job Purpose

The digital design engineer designs digital circuits of mixed signal IC with analog and application engineers, delivering block level and digital top-level to complete mixed signal IC design.

Principal Accountabilities

• Contribute system level IC design and design strategy from digital design perspective to achieve competitive product design and design strategy
• Design of optimized digital blocks meeting functional, cost and low power constraints and ensure spec. compliance
• Drive digital design verification, verification planning, feature extraction and verification test case development
• Support DfT strategy and implementation and verify test case
• Develop test vectors for production test

Key Performance Measures

• Capability to create block level design strategy from the IC specification, to fulfill cost, area and power requirements
• First time right design, on time and according to design specification
• Demonstrate knowledge sharing and mentoring of young analog design engineers
• Timely and accurate documentation

Knowledge, Skills and Experience

• Essential
  • At least 5 years’ experience in digital design
  • Fluent in either Verilog or VHDL TRL coding and IC design methodology
  • Proficiency in developing block and top-level timing constraints for STA and P&R handoff
  • Knowledge of lower-power digital design technique
  • Ability to work both independently and as part of a team
  • Good communication skill in English
• Desirable
  • Experience of digital interface design, such as I2C, I2S, I3C, SPI, SPMI, MIPI
  • Experience of Power management IC or charger IC development
  • Communication skill in Mandarin or Japanese

Qualification

Degree of electronics engineering or a related discipline